the sy100s834/l is low skew ( 1, 2, 4) or ( 2, 4, 8) clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the devices can be driven by either a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. in addition, by using the v bb output, a sinusoidal source can be ac-coupled into the device. if a single-ended input is to be used, the v bb output should be connected to the clk input and bypassed to ground via a 0.01 f capacitor. the v bb output is designed to act as the switching reference for the input of the sy100s834/l under single-ended input conditions. as a result, this pin can only source/sink up to 0.5ma of current. the function select (f sel ) input is used to determine what clock generation chip function is. when fs el input is low, sy100s834/l functions as a divide by 2, by 4 and by 8 clock generation chip. however, if fs el input is high, it functions as a divide by 1, by 2 and by 4 clock generation chip. this latter feature will increase the clock frequency by two folds. the common enable (en) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. upon start-up, the internal flip-flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as for multiple sy100s834/ls in a system. description 3.3v and 5v power supply options 50ps output-to-output skew synchronous enable/disable master reset for synchronization internal 75k ? input pull-down resistors available in 16-pin soic package features rev.: f amendment: /0 issue date: september, 1999 ( 1, 2, 4) or ( 2, 4, 8) clock generation chip clockworks sy100s834 SY100S834L final pin function clk differential clock inputs f sel function select en synchronous enable mr master reset v bb reference output q 0 differential 1 or 2 outputs q 1 differential 2 or 4 outputs q 2 differential 4 or 8 outputs pin names clk en mr function z l l divide zz h l hold q 0? x x h reset q 0? notes: z = low-to-high transition zz = high-to-low transition truth table f sel q 0 outputs q 1 outputs q 2 outputs l divide by 2 divide by 4 divide by 8 h divide by 1 divide by 2 divide by 4 pin configuration/block diagram soic top view v cc en f sel clk clk v bb mr v ee q 0 q 0 v cc q 1 q 1 v cc q 2 q 2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 q r q r 1 or 2 q q r r d 2 or 4 4 or 8 1
2 clockworks sy100s834 SY100S834L micrel t a = ?0 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit t plh propagation delay clk 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200 ps t phl to output mr 650 800 1010 650 800 1010 650 800 1010 650 800 1010 t skew within-device skew (2) 50 50 50 50 ps t s set-up time en 400 400 400 400 ps t h hold time en 200 200 200 200 ps v pp minimum input swing 250 250 250 250 mv v cmr common mode range (3) clk 1.3 0.4 1.4 0.4 1.4 0.4 1.4 0.4 v t r output rise/fall times 275 400 525 275 400 525 275 400 525 275 400 525 ps t f q (20% 80%) ac electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd notes: 1. parametric values specified at: 5 volt power supply range 100s834 series: -4.2v to -5.5v. 3 volt power supply range 100s834l series -3.0v to -3.8v. 2. within-device skew is specified for identical transition. 3. the cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min. and 1v. the lower end of the cmr range varies 1:1 with v ee . the numbers in the spec table assume a nominal v ee = 3.3v. note for pecl operation, the v cmr (min) will be fixed at 3.3v iv cmr (min)i. t a = ?0 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current 49 49 49 54 ma v bb output reference voltage -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 v i ih input high current 150 150 150 150 a dc electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd note: 1. parametric values specified at: 5 volt power supply range 100s834 series: -4.2v to -5.5v. 3 volt power supply range 100s834l series -3.0v to -3.8v.
3 clockworks sy100s834 SY100S834L micrel ordering package operating v ee range code type range (v) sy100s834zc z16-2 commercial -4.2 to -5.5 sy100s834zctr z16-2 commercial -4.2 to -5.5 SY100S834Lzc z16-2 commercial -3.0 to -3.8 SY100S834Lzctr z16-2 commercial -3.0 to -3.8 the en signal will freeze the internal clocks to the flip-flops on the first falling edge of clk after its assertion. the inte rnal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. the outputs wi ll transition to their next states in the same manner, time and relationship as they would have had the en signal not been asserted. timing diagram q 0 q 1 clk q 2 internal clock disabled f sel = 0 q 1 q 2 en f sel = 1 q 0 product ordering code ordering package operating v ee range code type range (v) sy100s834zi z16-2 industrial -4.2 to -5.5 sy100s834zitr z16-2 industrial -4.2 to -5.5 SY100S834Lzi z16-2 industrial -3.0 to -3.8 SY100S834Lzitr z16-2 industrial -3.0 to -3.8
4 clockworks sy100s834 SY100S834L micrel 16 lead soic .150" wide (z16-2) rev. 02 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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